Journal Title

Computers in Education Journal

Publication Date

2015

Abstract

Designing synchronous sequential circuits consisting of clocked storage elements such as flip-flops needs to observe stringent setup time and hold time constraints. If there is a timing violation, meaning the input data changes within the setup time and hold time window of the active clock edge, the results of the clocked storage elements could be unpredictable, a situation called metastable state. The cause and symptoms of metastable state are well established in the digital design literature. However, the effects of clock transition times such as rise time and fall time on the behavior of a synchronous sequential circuit are rarely discussed.

This paper presents an experiment to demonstrate that the transition time of a clock signal can also affect the results of a clocked storage element. Understanding this effect is crucial for designing more robust complex high-speed digital systems consisting of clocked storage elements.

Subjects

Digital design and applications; Electrical Engineering

Publication Information

Computers in Education Journal, 2015, Volume 6, Issue 1, 106-112.

© 2015 American Society for Engineering Education

Archived version is final published version.

Peer-Reviewed

Yes

Document Type

Journal Article

Included in

Engineering Commons

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